The present invention relates to integrated circuit memory devices and methods of operating same and, more particularly, to integrated circuit memory devices having normal and refresh modes of operation.
Integrated circuit memory devices may use partial activation techniques to reduce row access cycle times (tRC) and power consumption during normal modes of operation, which include writing and reading operations. Partial activation techniques typically utilize a single xe2x80x9cglobalxe2x80x9d word line (e.g., row select line) and bit line sense amplifier associated with one of a plurality of memory cell sub-blocks. However, such partial activation techniques are typically not feasible during other modes of operation, including refresh modes of operation. In particular, to reduce refresh cycle times, full activation techniques are used to activate global word lines across all memory cell sub-blocks within a row and also activate a plurality of bit line sense amplifiers associated with these plurality of memory cell sub-blocks. Such full activation techniques typically have greater power consumption requirements than partial activation techniques, particularly if boosted voltage levels are used.
FIG. 1 illustrates a conventional memory device that includes an XY array of memory cell sub-blocks 11 therein. As illustrated, the XY array of blocks 11 spans a plurality of rows (shown as X0, X1, X2, . . . ) and a plurality of columns (shown as Y0, Y1, Y2, Y3, Y0, Y1, . . . , Y3) of memory cell sub-blocks 11. A plurality of sub-word line driver control circuits PXID are also provided. Each of these control circuits PXID is configured to drive sub-word lines (SWD) within a pair of memory cell sub-blocks 11, in response to row select signals provided on row select lines (PXI) and column select signals provided on column select lines (YBLSEL). These row select signals may be referred to as global word line signals.
In FIG. 1, the illustrated control circuits PXID in row 0 of the XY array support respective pairs of blocks (shown as blocks (X0,Y0) and (X0,Y1)). These blocks are highlighted with cross-hatched shading. A row decoder 13 is provided for generating the row select signals and a column decoder 15 is provided for generating the column select signals. During a normal mode of operation, the sub-word lines (SWD) in the highlighted blocks are driven at boosted voltage levels (e.g., Vpp) that typically exceed an on-chip power supply voltage (e.g., Vdd). These sub-word lines are driven in response to a respective row select signal (PXI) and the illustrated plurality of column select signals (YBLSEL). Thus, only a relatively small number of select lines need to be driven during a normal mode of operation. However, during a refresh mode of operation, when full activation is present, it is typical that a much larger number of column select lines are driven to active levels to thereby enable the driving of sub-word lines in all of the blocks 11 within a selected row of the array. These active levels may be boosted voltage levels (e.g., Vpp) in some conventional memory devices. Because of the typically much larger number of column select lines that need to be driven to active levels during a refresh mode of operation, the power consumption requirements during a refresh mode of operation may be significantly greater than the power consumption requirements during a normal mode of operation. Accordingly, a significant disparity in power consumption requirements may be present when switching back and forth between normal and refresh modes of operation. This disparity may complicate the design of voltage boosting circuits that are active during the normal and refresh modes of operation.
Referring now to FIG. 2, another conventional method of operating a memory device in partial activation and full activation modes of operation will be described. In FIG. 2, twelve (12) memory cell sub-blocks 11 from a portion of a larger memory device are illustrated. These blocks 11 span a portion of rows 1-3 (shown as X1-X3) and a portion of columns 0-3 (shown as Y0-Y3). During a normal mode of operation, such as a write operation, the control circuit 21 (PXID) that drives the highlighted pair of blocks 11, is fully activated in response to a corresponding boosted column select signal (shown as YBLSEL1=Vpp) and a corresponding boosted row select signal (shown as PXI1=Vpp). In response to this full activation, the memory cells within the highlighted block 11 may be written with new data. This normal mode of operation, which includes partial activation of one or a selected few blocks 11 within a row, may require significantly less power consumption than a refresh operation that includes driving one row select line and all of the column select lines at boosted voltage levels, so that an entire row of the memory device may be refreshed. Thus, upon transitioning from a normal mode of operation to a refresh mode of operation, a relatively large number of column select lines (shown as YBLSEL0, YBLSEL1, . . . , YBLSEL3, YBLSEL0, . . . ) may have to be switched from ground reference voltages (e.g., Vss) to boosted voltage levels (e.g., Vpp) and this large amount of switching may consume significant amounts of power.
Accordingly, notwithstanding these conventional memory devices that support both normal and refresh modes of operation, there continues to be a need for memory devices that switch from one mode to another mode with reduced power consumption requirements and discrepancies.
Integrated circuit memory devices according to embodiments of the present invention improve power consumption requirements by reducing the amount of switching current needed by column decoders when switching from normal to refresh modes of operation (and vice versa). This reduction in switching current is achieved by essentially xe2x80x9cprechargingxe2x80x9d unused column select lines during a normal write operation so that they do not have to be precharged at a commencement of a refresh operation when they are used along with other column select lines to perform a write operation on an entire row of the memory device. This early precharging of the unused column select lines also facilitates balancing of the current demands placed on a column decoder (and boosting circuitry therein) during normal and refresh modes of operation.
According to some embodiments of the present invention, an XY array of memory cell sub-blocks is provided. The array includes first and second offset grids of sub-word line driver control circuits therein. Each of these sub-word line driver control circuits is configured to selectively activate a pair of the memory cell sub-blocks in response to a respective pair of active row and column select signals. Row and column decoder circuitry is also provided. The row and column decoder circuitry is configured drive a selected one of a plurality of row select lines associated with the first grid with an asserted row select signal and a plurality of column select lines associated with the second grid with asserted column select signals, during a normal write (or read) operation. The row and column decoder circuitry is further configured to drive a selected one (or selected ones) of a plurality of column select lines associated with the first grid with an asserted column select signal during the write operation, so that one or more pairs of selected sub-blocks may be activated to accept write data.
Still further embodiments of the present invention include methods of operating integrated circuit memory devices having XY arrays of memory cell sub-blocks therein In particular, these methods include driving a first plurality of column select lines, which are electrically coupled to a plurality of inactive sub-word line driver control circuits in a first row of the XY array, with column select signals having boosted voltage levels. This driving step is performed while simultaneously activating at least one sub-word line driver control circuit in a second row of the XY array during an operation to write data into a memory cell sub-block that is electrically coupled to the activated sub-word line driver control circuit. This driving step is followed by the step of driving a second plurality of column select lines, which are electrically coupled to a plurality of sub-word line driver control circuits in the second row of the XY array, with boosted column select signals during a refresh operation. During the refresh mode of operation, the first plurality of column select lines are maintained at their boosted voltage levels.
Still further embodiments of the present invention include methods that cover driving a plurality of column select lines that extend across the XY array with asserted column select signals that are received by a plurality of sub-word line driver control circuits in the XY array. A first row select line, which extends across the XY array, is then driven with an asserted row select signal that is received by at least two of the plurality of sub-word line driver control circuits that are associated with a first row of the XY array, during a write operation. This step is performed concurrently with deasserting a column select signal received by one of the at least two of the plurality of sub-word line driver control circuits in the first row.